Type Alias avr_device::atmega2560::adc::admux::MUX_W

pub type MUX_W<'a, const O: u8> = FieldWriterSafe<'a, u8, ADMUX_SPEC, u8, MUX_A, 5, O>;

Field MUX writer - Analog Channel and Gain Selection Bits

Aliased Type

struct MUX_W<'a, const O: u8> { /* private fields */ }

Implementations

impl<'a, const O: u8> MUX_W<'a, O>

pub fn adc0(self) -> &'a mut W

ADC Single Ended Input pin 0

pub fn adc1(self) -> &'a mut W

ADC Single Ended Input pin 1

pub fn adc2(self) -> &'a mut W

ADC Single Ended Input pin 2

pub fn adc3(self) -> &'a mut W

ADC Single Ended Input pin 3

pub fn adc4(self) -> &'a mut W

ADC Single Ended Input pin 4

pub fn adc5(self) -> &'a mut W

ADC Single Ended Input pin 5

pub fn adc6(self) -> &'a mut W

ADC Single Ended Input pin 6

pub fn adc7(self) -> &'a mut W

ADC Single Ended Input pin 7

pub fn adc0_adc0_10x(self) -> &'a mut W

ADC Differential Inputs Postive pin 0 Negative pin 0 10x Gain

pub fn adc1_adc0_10x(self) -> &'a mut W

ADC Differential Inputs Postive pin 1 Negative pin 0 10x Gain

pub fn adc0_adc0_200x(self) -> &'a mut W

ADC Differential Inputs Postive pin 0 Negative pin 0 200x Gain

pub fn adc1_adc0_200x(self) -> &'a mut W

ADC Differential Inputs Postive pin 1 Negative pin 0 200x Gain

pub fn adc2_adc2_10x(self) -> &'a mut W

ADC Differential Inputs Postive pin 2 Negative pin 2 10x Gain

pub fn adc3_adc2_10x(self) -> &'a mut W

ADC Differential Inputs Postive pin 3 Negative pin 2 10x Gain

pub fn adc2_adc2_200x(self) -> &'a mut W

ADC Differential Inputs Postive pin 2 Negative pin 2 200x Gain

pub fn adc3_adc2_200x(self) -> &'a mut W

ADC Differential Inputs Postive pin 3 Negative pin 2 200x Gain

pub fn adc0_adc1_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 0 Negative pin 1 1x Gain

pub fn adc1_adc1_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 1 Negative pin 1 1x Gain

pub fn adc2_adc1_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 2 Negative pin 1 1x Gain

pub fn adc3_adc1_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 3 Negative pin 1 1x Gain

pub fn adc4_adc1_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 4 Negative pin 1 1x Gain

pub fn adc5_adc1_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 5 Negative pin 1 1x Gain

pub fn adc6_adc1_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 6 Negative pin 1 1x Gain

pub fn adc7_adc1_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 7 Negative pin 1 1x Gain

pub fn adc0_adc2_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 0 Negative pin 2 1x Gain

pub fn adc1_adc2_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 1 Negative pin 2 1x Gain

pub fn adc2_adc2_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 2 Negative pin 2 1x Gain

pub fn adc3_adc2_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 3 Negative pin 2 1x Gain

pub fn adc4_adc2_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 4 Negative pin 2 1x Gain

pub fn adc5_adc2_1x(self) -> &'a mut W

ADC Differential Inputs Postive pin 5 Negative pin 2 1x Gain

pub fn adc_vbg(self) -> &'a mut W

Internal Reference (VBG)

pub fn adc_gnd(self) -> &'a mut W

0V (GND)